TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 157

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
12. Time Base Timer (TBT)
12.1
12.1.1
12.1.2
Time base timer control register
(0x0039)
TBTCR
a time base timer interrupt (INTTBT) in a certain cycle.
The time base timer generates the time base for key scanning, dynamic display and other processes. It also provides
Note 1: fcgck : Gear clock [Hz], fs : Low-frequency clock [Hz]
Note 2: When the operation is changed to the STOP mode, TBTCR<TBTEN> is cleared to "0" and TBTCR<TBTCK> maintains
Note 3: TBTCR<TBTCK> should be set when TBTCR<TBTEN> is "0".
Time Base Timer
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
The time base timer is controlled by the time base timer control register (TBTCR).
Configuration
Control
Read/Write
TBTEN
TBTCK
Bit Symbol
After reset
the value.
22
20
15
13
12
10
11
or fs/2
or fs/2
fcgck/2
or fs/2
or fs/2
or fs/2
or fs/2
or fs/2
15
13
8
6
5
4
3
8
Enables/disables the time base tim-
er interrupt requests
Selects the time base timer interrupt
frequency
Unit: [Hz]
TBTCK
Figure 12-1 Time Base Timer Configuration
R
7
0
-
3
TBTCR
Source clock
R
6
0
-
TBTEN
R
5
0
0: Disables generation of interrupt request signals
1: Enables generation of interrupt request signals
TBTCK
Page 141
Falling edge
-
detector
000
001
010
011
100
101
110
111
R
4
0
-
DV9CK = 0
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
NORMAL 1/2, IDLE 1/2 mode
22
20
15
13
12
11
10
8
TBTEN
R/W
3
0
DV9CK = 1
Reserved
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
2
0
15
13
8
6
5
4
3
INTTBT
Interrupt request
IDLE0, SLEEP0
Release request
TBTCK
R/W
1
0
SLOW1/2, SLEEP1
TMP89FS60
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
mode
fs/2
fs/2
15
13
0
0