TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 293

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA002
I
Serial bus interface data buffer register
2
C bus address register
SBI0DBR
(0x0024)
(0x0025)
I2C0AR
Note 1: Don't set I2C0AR<SA> to "0x00". If it is set to "0x00", the slave address is deemed to be matched when the I
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
Note 1: Write the transmit data beginning with the most significant bit (bit 7).
Note 2: SBI0DBR has individual writing and reading buffers, and written data cannot be read out. Therefore, SBI0DBR must not
Note 3: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
Note 4: To set SBI0CR2<PIN> to "1" by writing the dummy data to SBI0DBR, write 0x00. Writing any data other than 0x00 causes
Note 5: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
Read/Write
Read/Write
Bit Symbol
Bit Symbol
After reset
standard start byte ("0x01") is received in the slave mode.
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
and SBI0SR2 registers are initialized.
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
After reset
be accessed by using a read-modify-write instruction, such as a bit operation.
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
an improper value in the subsequently received data.
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
R/W
7
0
7
0
R/W
6
0
6
0
R/W
5
0
5
0
Page 277
R/W
SA
4
0
4
0
SBI0DBR
R/W
R/W
3
0
3
0
R/W
2
0
2
0
R/W
1
0
1
0
TMP89FS60
ALS
R/W
0
0
0
0
2
C bus