TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 219

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA005
14.4.7.2
PWM1 pin output
(TFF1=“1”)
PWM1 pin output
(TFF1=“0”)
INTTC00 interrupt
request
INTTC01 interrupt
request
Cycle
PWM1 pin output
(TFF1=“1”)
PWM1 pin output
(TFF1=“0”)
INTTC00 interrupt
request
INTTC01 interrupt
request
Cycle
When a match between the lower 8 bits of the up counter value and the value set to PWMDUTY is detected,
the output of the PWM1 pin is reversed. When T01MOD<TFF1> is "0", the PWM1 pin changes from the "L"
to "H" level. When T01MOD<TFF1> is "1", the PWM1 pin changes from the "H" to "L" level.
in specific cycles of the duty pulse. In other words, the PWM1 pin output is reversed at the timing of
PWMDUTY+1. When T00MOD<TFF0> is "0", the period of the "L" level becomes longer than the value
set to PWMDUTY by 1 source clock. When T00MOD<TFF0> is "1", the period of the "H" level becomes
longer than the value set to PWMDUTY by 1 source clock. This function allows 16 cycles of output pulses
to be handled with a resolution nearly equivalent to 12 bits.
occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM1 pin is reversed.
When T01MOD<TFF1> is "0", the PWM1 pin changes from the "H" to "L" level. When T01MOD<TFF1>
is "1", the PWM1 pin changes from the "L" to "H" level. At this time, an INTTC00 interrupt request is
generated (an INTTC00 interrupt request is generated each time an overflow occurs.) An INTTC01 interrupt
request is generated at the 16 × n-th overflow (n=1, 2, 3...). Subsequently, the up counter continues counting
up.
Setting T001CR<T01RUN> to "1" allows the up counter to increment based on the selected source clock.
If any of PWMAD3 to 0 is "1", an additional pulse that corresponds to 1 count of the source clock is inserted
No additional pulse is inserted when PWMAD3 to 0 are all "0".
Subsequently, the up counter continues counting up. When the up counter value reaches 256, an overflow
Timer start
Timer start
Operations
1
1
Figure 14-13 Examples of Inserting Additional Pulses
2
2
Additional
pulse
3
3
4
4
Additional
When PWMAD0 = “1” and PWMAD2 = “1”
pulse
5
5
6
6
When PWMAD1=“1”
Additional
pulse
7
7
Page 203
8
8
Additional
pulse
9
9
10
10
Additional
11
11
pulse
12
12
Additional
13
13
pulse
14
14
Additional
15
15
pulse
16
16
TMP89FS60
Timer stop
Timer stop
17
17