TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 41

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3.5.3
states in effect before the system was stopped are held with low power consumption.
the same as the states when a reset is released. For operations of the peripheral circuits in the STOP mode,
refer to the section of each peripheral circuit.
operation returns to the mode that was active before the STOP mode, and the operation is restarted by the
instruction that follows the STOP mode activation instruction.
(5)
(6)
In this mode, all the operations in the system, including the oscillation circuits, are stopped and the internal
In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or become
The STOP mode is activated by setting SYSCR1<STOP> to "1".
The STOP mode is released by the STOP mode release signals. After the warm-up time has elapsed, the
STOP mode
returns to the NORMAL2 mode after this mode is released.
timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock
(fs).
For operations of the peripheral circuits in the SLEEP1 mode, refer to the section of each peripheral
circuit.
operation returns to the SLOW1 mode after this mode is released.
using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits
stop.
or become the same as the states when a reset is released. For operations of the peripheral circuits in the
SLEEP0 mode, refer to the section of each peripheral circuit.
operation returns to the SLOW1 mode after this mode is released.
circuits except the time base timer.
The IDLE2 mode can be activated and released in the same way as for the IDLE1 mode. The operation
In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watchdog
In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is released.
The SLEEP1 mode can be activated and released in the same way as for the IDLE1 mode. The
In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
In this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates
In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activated
The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The
In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the peripheral
SLEEP1 mode
SLEEP0 mode
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TMP89FS60