TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 47

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3.6.2
Note:When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up
counter.
interrupts. The following states are maintained during these modes.
The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and maskable
IDLE1/2 and SLEEP1 modes
1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to operate.
2. The data memory, the registers, the program status word and the port output latches are all held
3. The program counter holds the address of the instruction 2 ahead of the instruction which starts
(Normal release mode)
in the status in effect before IDLE1/2 or SLEEP1 mode was started.
the IDLE1/2 or SLEEP1 mode.
Figure 2-10 IDLE1/2 and SLEEP 1 Modes
No
No
No
which follows the IDLE1/2 mode
Starting IDLE1/2 mode or
Execution of the instruction
SLEEP1 mode by an
Interrupt processing
or SLEEP1 mode start
CPU and WDT stop
Reset input
instruction
Page 31
instruction
IMF = "1"
Interrupt
request
Yes
Yes
No
(Interrupt release mode)
Yes
Reset
TMP89FS60