TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 270

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TMP89xy60UG/FG

Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP89xy60UG/FG

Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
17.4
Functions
RA001
SCLK0 pin
SO0 pin
SI0 pin
Note:When an external clock input is used, 4/fcgck or longer is needed between the receive edge at the 8th
bit and the transfer edge at the first bit of the next transfer.
SLCK0 pin
SO0 pin
SI0 pin
SCLK0 pin
SO0 pin
SI0 pin
C6
A6
C7
A7
Figure 17-3 Interval time between bytes
D0
B0
Figure 17-2 Transfer Edge
When SIOCR<SIOEDG>=“0”
When SIOCR<SIOEDG>=“1”
R0
R0
T0
T0
D1
B1
R1
R1
T1
T1
Page 254
D2
B2
T2
R2 R3 R4 R5 R6 R7
T2
R2 R3 R4 R5 R6 R7
T3
T3
Trailing edge at the
8th bit (receive edge)
T4
T4
Symbol
tBI
T5
T5
Interval time between bytes
T6
T6
tBI
T7
T7
Name
Leading edge at the
1st bit (transmit edge)
Minimum time
4/fcgck
TMP89FS60

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