TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 70

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

3.4
Maskable Interrupt Priority Change Function
RA003
3.4
Interrupt priority change control register 1
Interrupt priority change control register 2
Interrupt priority change control register 3
(0x0FF0)
(0x0FF1)
(0x0FF2)
ILPRS1
ILPRS2
ILPRS3
priorities 5 to 28. Interrupt priorities can be changed by the interrupt priority change control register (ILPRS1 to
ILPRS6). To raise the interrupt priority, set the Level to a larger number. To lower the interrupt priority, set the Level
to a smaller number. When different maskable interrupts are generated simultaneously at the same level, the interrupt
with higher basic priority is processed preferentially. For example, when the ILPRS1 register is set to 0xC0 and
interrupts IL4 and IL7 are generated at the same time, IL7 is preferentially processed (provided that EF4 and EF7 have
been enabled).
Maskable Interrupt Priority Change Function
The priority of maskable interrupts (IL4 to IL27) can be changed to four levels, Levels 0 to 3, regardless of the basic
After reset is released, all maskable interrupts are set to priority level 0 (the lowest priority).
Note:In the main program, before manipulating the interrupt priority change control register (ILPRS1 to 6), be sure to
clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction).
Set the IMF to "1" as required after operating ILPRS1 to 6 (Enable interrupt by EI instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally.
However, if using multiple interrupt in the interrupt service routine, manipulate ILPRS1 to 6 before setting the
IMF to "1".
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
IL07P
IL06P
IL05P
IL04P
IL11P
IL10P
IL09P
IL08P
IL15P
IL14P
IL13P
IL12P
Sets the interrupt priority of IL7.
Sets the interrupt priority of IL6.
Sets the interrupt priority of IL5.
Sets the interrupt priority of IL4.
Sets the interrupt priority of IL11.
Sets the interrupt priority of IL10.
Sets the interrupt priority of IL9.
Sets the interrupt priority of IL8.
Sets the interrupt priority of IL15.
Sets the interrupt priority of IL14.
Sets the interrupt priority of IL13.
Sets the interrupt priority of IL12.
7
0
7
0
7
0
IL07P
IL11P
IL15P
R/W
R/W
R/W
6
0
6
0
6
0
5
0
5
0
5
0
Page 54
00:
01:
10:
11:
00:
01:
10:
11:
00:
01:
10:
11:
IL06P
IL10P
IL14P
R/W
R/W
R/W
Level 0 (lower priority)
Level 1
Level 2
Level 3 (higher priority)
Level 0 (lower priority)
Level 1
Level 2
Level 3 (higher priority)
Level 0 (lower priority)
Level 1
Level 2
Level 3 (higher priority)
4
0
4
0
4
0
3
0
3
0
3
0
IL05P
IL09P
IL13P
R/W
R/W
R/W
2
0
2
0
2
0
1
0
1
0
1
0
TMP89FS60
IL04P
IL08P
IL12P
R/W
R/W
R/W
0
0
0
0
0
0