TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 353

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA006
sINTWDT:
sINTSWI:
sRAMprogEnd:
Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more
Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is generated
than three machine cycles or arrange write instructions in such a way that they are generated at intervals
of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions are executed
at intervals of two machine cycles, the flash memory command sequence will not be transmitted properly,
and a malfunction may occur.
in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals
of three or more machine cycles; machine cycles are counted from when the last xth bus write cycle is
generated to when each instruction is generated. Three NOP instructions are normally used. If the interval
between instructions is short, the toggle bit does not operation correctly.
LD
LD
CMP
J
LD
RETN
NOP
IX,0xF000
A,(IX)
A,(IX)
NZ,sINTWDT
(SYSCR2),0x10
Page 337
; Loop until the read values become the same
; Generate system clock reset
TMP89FS60