TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 7
TMP89xy60UG/FG
Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP89XY60UGFG.pdf
(432 pages)
Specifications of TMP89xy60UG/FG
Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
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2. CPU Core
Precaution for Using the Emulation Chip (Development Tool)
TMP89FS60
1.1 Features......................................................................................................................................1
1.2 Pin Assignment..........................................................................................................................3
1.3 Block Diagram...........................................................................................................................4
1.4 Pin Names and Functions..........................................................................................................5
2.1 Configuration.............................................................................................................................9
2.2 Memory space............................................................................................................................9
2.3 System clock controller...........................................................................................................15
2.4 Reset Control Circuit...............................................................................................................38
2.2.1
2.2.2
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4.1
2.4.2
2.4.3
2.4.4
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.3.3.1
2.3.3.2
2.3.3.3
2.3.4.1
2.3.4.2
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.4.4.1
2.4.4.2
2.4.4.3
2.4.4.4
2.4.4.5
2.4.4.6
2.4.4.7
Code area.............................................................................................................................................................................9
Data area............................................................................................................................................................................13
Configuration.....................................................................................................................................................................15
Control...............................................................................................................................................................................15
Functions............................................................................................................................................................................17
Warm-up counter...............................................................................................................................................................20
Operation mode control circuit..........................................................................................................................................22
Operation Mode Control....................................................................................................................................................27
Configuration.....................................................................................................................................................................38
Control...............................................................................................................................................................................38
Functions............................................................................................................................................................................40
Reset Signal Generating Factors........................................................................................................................................42
RAM
BOOTROM
Flash
SFR
RAM
BOOTROM
Flash
Clock generator
Clock gear
Timing generator
Warm-up counter operation when the oscillation is enabled by the hardware
Warm-up counter operation when the oscillation is enabled by the software
Single-clock mode
Dual-clock mode
STOP mode
Transition of operation modes
STOP mode
IDLE1/2 and SLEEP1 modes
IDLE0 and SLEEP0 modes
SLOW mode
Power-on reset
External reset input (RESET pin input)
Voltage detection reset
Watchdog timer reset
System clock reset
Trimming data reset
Flash standby reset
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