TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 44

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
Note:
SSTOPH:
PINT5:
SINT5:
When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that
generated the main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>.
Example: Starting the STOP mode from NORMAL mode after testing P00 port.
Example: Starting the STOP mode from the SLOW mode with an INT5 interrupt
Note:During the STOP period (from the start of the STOP mode to the end of the warm-up), due to
LD
TEST
J
LD
LD
DI
SET
TEST
J
LD
LD
LD
DI
SET
RETI
(Warm-up time at release of the STOP mode is about 300μs at fc= 8MHz.)
(Warm-up time at release of the STOP mode is about 450ms at fs=32.768 kHz.)
1. Release by the STOP pin
changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may
be accepted immediately after the STOP mode is released. Before starting the STOP mode,
therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear
unnecessary interrupt latches.
edge-sensitive release mode, either of which can be selected at SYSCR1<RELM>.
Release the STOP mode by using the STOP pin.
The STOP mode release by the STOP pin includes the level-sensitive release mode and the
The STOP pin is also used as the P11 port and the INT5 (external interrupt input 5) pin.
(SYSCR1), 0x40
(P0PRD). 5
F, SSTOPH
(WUCCR), 0x01
(WUCDR),0x26
(SYSCR1).7
(P0PRD).5
F, SINT5
(SYSCR1), 0x40
(WUCCR), 0x03
(WUCDR),0xE8
(SYSCR1).7
- Level-sensitive release mode
Note: When the STOP mode is released, the warm-up counter source clock automatically changes
the long term battery backup.
is high, the STOP mode does not start. Thus, to start the STOP mode in the level-sensitive
release mode, it is necessary for the program to first confirm that the STOP pin input is
low.
The STOP mode is released by setting the STOP pin high.
Setting SYSCR1<RELM> to "1" selects the level-sensitive release mode.
This mode is used for the capacitor backup when the main power supply is cut off and
Even if an instruction for starting the STOP mode is executed while the STOP pin input
This can be confirmed by testing the port by the software or using interrupts
to the clock that generated the main system clock when the STOP mode was started, regard-
less of WUCCR<WUCSEL>.
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;Sets up the level-sensitive release mode
;Wait until STOP pin becomes L level.
;WUCCR<WUCDIV> = 00 (No division) (Note)
;Sets the warm-up time
;300μs / 8μs = 37.5 → round up to 0x26
;IMF = 0
;Starts the STOP mode
;To reject noise, the STOP mode does not start
;if the STOP pin input is high.
;Sets up the level-sensitive release mode
;WUCCR<WUCDIV> = 00 (No division) (Note)
;Sets the warm-up time
;450 ms/1.953 ms = 230.4 → round up to 0xE8
;IMF = 0
;Starts the STOP mode
TMP89FS60