TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 276

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

17.5
Transfer Modes
RA001
17.5.2
17.5.2.1
17.5.2.2
17.5.2.3
17.5.2.4
The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".
8-bit Receive Mode
SIO0CR<SIOEDG>, a transfer format at SIO0CR<SIODIR> and a serial clock at SIO0CR<SIOCKS>. To
use the internal clock as the serial clock, select an appropriate serial clock at SIO0CR<SIOCKS>. To use an
external clock as the serial clock, set SIO0CR<SIOCKS> to "111".
progress, or when SIO0SR<SIOF> is "1". Make these settings while the serial communication is stopped.
While the serial communication is in progress (SIO0SR<SIOF>="1"), only writing "00" to SIO0CR<SIOM>
or writing "0" to SIO0CR<SIOS> is valid.
from the SI0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS and SIODIR>.
the external clock operation, an external clock must be supplied to the SCLK0 pin.
INTSIO0 interrupt request is generated. The receive completion flag SIO0SR<REND> is set to "1".
SIO0BUF (automatic wait). At this time, SIO0SR<SEF> is set to "0". By reading the receive data from
SIO0BUF, SIO0SR<SEF> is set to "1", the serial clock output is restarted and the receive operation continues.
data from SIO0BUF. In this case, data must be read from SIO0BUF before the subsequent data has been fully
received. If the subsequent data is received completely before reading data from SIO0BUF, the overrun error
flag SIO0SR<OERR> is set to "1". When an overrun error has occurred, set SIO0CR<SIOM> to "00" to abort
the receive operation. The data received at the occurrence of an overrun error is discarded, and SIO0BUF
holds the data value received before the occurrence of the overrun error.
SIO0SR.
operation is not in progress, the operation is stopped immediately. Unlike the transmit mode, no INTSIO0
interrupt request is generated in this state.
(reserved stop). At this time, an INTSIO0 interrupt request is generated.
As in the case of the transmit mode, before starting the receive operation, select the transfer edges at
The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".
Reception is started by setting SIO0CR<SIOS> to "1".
Writing data to SIO0CR<SIOEDG, SIOCKS and SIODIR> is invalid when the serial communication is in
Reception is started by setting SIO0CR<SIOS> to "1". External serial data is taken into the shift register
In the internal clock operation, the serial clock of the selected baud rate is output from the SCLK0 pin. In
By setting SIO0CR<SIOS> to "1", SIO0SR<SIOF and SEF> are automatically set to "1".
When the data reception is completed, the data is transferred from the shift register to SIO0BUF and an
In the operation with the internal clock, the serial clock output is stopped until the receive data is read from
In the operation with an external clock, data can be continuously received without reading the received
SIO0SR<REND> is cleared to "0" by reading data from SIO0BUF. SIO0SR<OERR> is cleared by reading
Set SIO0CR<SIOS> to "0" to stop the receive operation. When SIO0SR<SEF> is "0", or when the shift
When SIO0SR<SEF> is "1", the operation is stopped after the 8-bit data has been completely received
Setting
Starting the receive operation
Operation on completion of reception
Stopping the receive operation
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TMP89FS60