TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 324

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

20.3
Functions
RA002
20.3
20.3.1
20.3.2
mode in which AD conversion is performed repeatedly.
The 10-bit AD converter operates in either single mode in which AD conversion is performed only once or repeat
ADCCR1<ADRS> is automatically cleared after the start of AD conversion. As AD conversion starts,
ADCCR2<ADBF> is set to "1". It is cleared to "0" if AD conversion is finished or if AD conversion is forced to
stop.
and ADCDRH), ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt (INTADC) is gener-
ated. The AD converted value registers (ADCDRL and ADCDRH) should be usually read according to the
INTADC interrupt processing routine. If the upper side (ADCDRH) of the AD converted value register is read,
ADCCR2<EOCF> is cleared to "0".
the start of AD conversion, ADCCR1<ADRS> is automatically cleared. After the first AD conversion is finished,
the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH), ADCCR2<EOCF>
is set to "1", and the AD conversion finished interrupt (INTADC) is generated. After this interrupt is generated,
the second (next) AD conversion starts immediately.
Functions
ADCCR1<ADRS>
ADCCR2<ADBF>
Status of ADCDRL
and ADCDRH
ADCCR2<EOCF>
INTADC interrupt
request
Read of ADCDRH
Read of ADCDRL
In single mode, the voltage at a designated analog input pin is AD converted only once.
Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "01" allows AD conversion to start.
After AD conversion is finished, the conversion result is stored in the AD converted value registers (ADCDRL
In repeat mode, the voltage at an analog input pin designated at ADCCR1<SAIN> is AD converted repeatedly.
Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "11" allows AD conversion to start. After
Single mode
Repeat mode
Note:Do not perform the following operations on the ADCCR1 register when AD conversion is being executed
(ADCCR2<ADBF>="1"). If the following operations are performed, there is the possibility that AD con-
version may not be executed properly.
・ Changing the ADCCR1<SAIN> setting
・ Setting ADCCR1<AINEN> to "0"
・ Changing the ADCCR1<AMD> setting (except a forced stop by setting AMD to "00")
・ Setting ADCCR1<ADRS> to "1"
AD conversion start
Indeterminate
Figure 20-2 Single Mode
Result of the first conversion
Read of conversion result
Read of conversion result
Page 308
AD conversion start
Result of the second conversion
Read of conversion result
Read of conversion result
Clearing EOCF based on
the conversion result
TMP89FS60