TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 48

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
2.3.6.3
base timer control register (TBTCR). The following states are maintained during the IDLE0 and SLEEP0
modes:
(1)
(2)
The IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time
IDLE0 and SLEEP0 modes
to "1", which releases IDLE1/2 and SLEEP1 modes.
SYSCR2<IDLE> remains cleared and the IDLE1/2 or SLEEP1 mode will not be started.
modes are selected at the interrupt master enable flag (IMF). After releasing IDLE1/2 or SLEEP1 mode,
SYSCR2<IDLE> is automatically cleared to "0" and the operation mode is returned to the mode pre-
ceding the IDLE1/2 or SLEEP1 mode.
and a reset by the voltage detection circuits. After releasing the reset, the warm-up starts. After the
warm-up is completed, the NORMAL1 mode becomes active.
・ The timing generator stops the clock supply to the peripheral circuits except the time base timer.
・ The data memory, the registers, the program status word and the port output latches are all held
・ The program counter holds the address of the instruction 2 ahead of the instruction which starts
Note 1: When a watchdog timer interrupt is generated immediately before the IDLE1/2 or SLEEP1 mode
Note 2: Before starting the IDLE1/2 or SLEEP1 mode, enable the interrupt request signals to be generated
After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag (EF)
To start the IDLE1/2 or SLEEP1 mode, set SYSCR2<IDLE> to "1".
If the release condition is satisfied when it is attempted to start the IDLE1/2 or SLEEP1 mode,
The IDLE1/2 and SLEEP1 modes include a normal release mode and an interrupt release mode. These
The IDLE1/2 and SLEEP1 modes are also released by a reset by the RESET pin, a power-on reset
Start the IDLE1/2 and SLEEP1 modes
Release the IDLE1/2 and SLEEP1 modes
・ Normal release mode (IMF = "0")
・ Interrupt release mode (IMF = "1")
in the states in effect before the IDLE0 or SLEEP0 mode was started.
the IDLE0 or SLEEP0 mode.
interrupt enable flag (EF) is "1". The operation is restarted by the instruction that follows the
IDLE1/2 or SLEEP1 mode start instruction. Normally, the interrupt latch (IL) of the interrupt
source used for releasing must be cleared to "0" by load instructions.
interrupt enable flag (EF) is "1". After the interrupt is processed, the operation is restarted by
the instruction that follows the IDLE1/2 or SLEEP1 mode start instruction.
is started, the watchdog timer interrupt will be processed but the IDLE1/2 or SLEEP1 mode will
not be started.
to release the IDLE1/2 or SLEEP1 mode and set the individual interrupt enable flag.
The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual
The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual
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TMP89FS60