TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 93

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA000
5.3.3
5.3.4
Note:
8-bit up counter value
When WDCTR<WDTW> is “00”
When WDCTR<WDTW> is “01”
When WDCTR<WDTW> is “10”
When WDCTR<WDTW> is “11”
request signal occurs, depending on the WDCTR<WDTOUT> setting.
counter continues counting, even after the overflow has occurred.
SLEEP mode, and restarts counting up after the STOP/IDLE/SLEEP mode is released. To prevent the 8-bit up
counter from overflowing immediately after the STOP/IDLE/SLEEP mode is released, it is recommended to
clear the 8-bit up counter before the operation mode is changed.
When a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is
already accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put
on hold. Therefore, if watchdog timer interrupts are generated continuously without execution of the RETN in-
struction, too many levels of nesting may cause a malfunction of the microcontroller.
Setting the overflow time of the 8-bit up counter
Setting an overflow detection signal of the 8-bit up counter
WDCTR<WDTT> sets the overflow time of the 8-bit up counter.
When the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt
If the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog
The watchdog timer temporarily stops counting up in the STOP mode (including warm-up) or in the IDLE/
WDCTR<WDTOUT> selects a signal to be generated when the overflow of the 8-bit up counter is detected.
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore,
1. When the watchdog timer interrupt request signal is selected (when WDCTR<WDTOUT> is "0")
Figure 5-3 WDCTR<WDTW> and the 8-bit up Counter Clear Time
Table 5-1 Watchdog Timer Overflow Time (fcgck=8.0 MHz; fs=32.768 kHz)
the first overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a
maximum of 1 source clock. The 8-bit up counter must be cleared within a period of the overflow time
minus 1 source clock cycle.
when the 8-bit up counter overflows.
of the interrupt master enable flag (IMF) setting.
Releasing WDCTR<WDTOUT> to "0" causes a watchdog timer interrupt request signal to occur
A watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regardless
WDTT
00
01
10
11
0xFF 0x00 0x01
Outside the clear time
DV9CK = 0
131.07 m
524.29 m
32.77 m
2.097
Outside the clear time
NORMAL mode
0x3F
Watchdog timer overflow time [s]
Page 77
0x40
Outside the
clear time
Clear time
DV9CK = 1
250.00 m
62.50 m
1.000
4.000
0x7F 0x80
Clear time
0xBF 0xC0
250.00 m
62.50 m
Clear time
SLOW
mode
1.000
4.000
Clear time
0xFF 0x00
TMP89FS60