AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 164

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Table 51. FPSLIC Interface Timing Information
Note:
164
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
IXG4
IXG5
IXC
IXI
CFIR
CFIW
CFIS
FIRQ
IFS
FRWS
FAS
FDWS
FDRS
1. Insertion delays are specified from XTAL2. These delays are more meaningful because the XTAL1-to-XTAL2 delay is sensi-
AT94K Series FPSLIC
tive to system loading on XTAL2. If it is necessary to drive external devices with the system clock, devices should use
XTAL2 output pin. Remember that XTAL2 is inverted in comparison to XTAL1.
Parameter
Clock Delay From XTAL2 Pad
to GCK_5 Access to FPGA Core
Clock Delay From XTAL2 Pad
to GCK_6 Access to FPGA Core
Clock Delay From XTAL2 Pad
to AVR Core Clock
Clock Delay From XTAL2 Pad
to AVR I/O Clock
AVR Core Clock to FPGA
I/O Read Enable
AVR Core Clock to
FPGA I/O Write Enable
AVR Core Clock to
FPGA I/O Select Active
FPGA Interrupt Net
Propagation Delay to AVR Core
FPGA SRAM Clock to
On-chip SRAM
FPGA SRAM Write
Stobe to On-chip SRAM
FPGA SRAM Address Valid to
On-chip SRAM Address Valid
FPGA Write Data Valid
to On-chip SRAM Data Valid
On-chip SRAM Data Valid to
FPGA Read Data Valid
Minimum
(1)
3.6
3.9
2.8
3.5
5.3
5.2
6.3
0.2
6.1
4.4
5.4
1.3
0.2
3.3V Commercial ± 10%
Typical
4.8
5.2
3.7
4.7
6.6
6.6
7.8
0.2
7.7
5.5
6.7
1.7
0.2
Maximum
7.6
8.1
6.3
7.5
7.9
7.9
9.4
0.3
7.7
5.5
6.7
2.0
0.2
Minimum
3.4
3.6
2.5
3.2
4.4
4.4
5.3
0.1
4.9
3.7
4.3
1.3
0.2
3.3V Industrial ± 10%
Typical
4.8
5.2
3.7
4.7
6.6
6.6
7.8
0.2
7.7
5.5
6.7
1.7
0.2
Rev. 1138F–FPSLI–06/02
Maximum
11.0
7.9
8.8
6.9
7.8
9.2
9.2
0.3
7.7
5.5
6.7
2.0
0.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns