AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 89

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
• Bits 5,4 - COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0
The COMn1 and COMn0 control bits determine any output pin action following a compare
match in Timer/Counter0 or Timer/Counter2. Output pin actions affect pins PE1(OC0) or
PE3(OC2). This is an alternative function to an I/O port, and the corresponding direction con-
trol bit must be set (one) to control an output pin. The control configuration is shown in Table
21.
Table 21. Compare Output Mode Select
Notes:
• Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match
When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is reset to
$00 in the CPU clock-cycle after a compare match. If the control bit is cleared, Timer/Counter
continues counting and is unaffected by a compare match. When a prescaling of 1 is used,
and the compare register is set to C, the timer will count as follows if CTC0/CTC2 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1,
...
In PWM mode, this bit has a different function. If the CTC0 or CTC2 bit is cleared in PWM
mode, the Timer/Counter acts as an up/down counter. If the CTC0 or CTC2 bit is set (one), the
Timer/Counter wraps when it reaches $FF. Refer to page 91 for a detailed description.
• Bits 2,1,0 - CS02, CS01, CS00/ CS22, CS21, CS20: Clock Select Bits 2,1 and 0
The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter0 and
Timer/Counter2, see Table 22 and Table 23.
Table 22. Clock 0 Prescale Select
CS02
COMn1
0
0
0
0
1
1
1
1
0
0
1
1
1. In PWM mode, these bits have a different function. Refer to Table 24 for a detailed
2. n = 0 or 2
description.
CS01
0
0
1
1
0
0
1
1
COMn0
0
1
0
1
CS00
0
1
0
1
0
1
0
1
Description
Timer/Counter disconnected from output pin OCn
Toggles the OCn
Clears the OCn
Sets the OCn
Description
Stop, the Timer/Counter0 is stopped
CK
CK/8
CK/64
CK/256
CK/1024
External pin PE0(T0), falling edge
External pin PE0(T0), rising edge
(1)
(2)
(2)
output line (to one).
(2)
AT94K Series FPSLIC
output line (to zero).
output line.
(2)
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