AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 61

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Reset Sources
Figure 35. Reset Logic
Rev. 1138F–FPSLI–06/02
AVR RESET
RESET/
SFTCR
BIT 0
CONFIG
LOGIC
FPGA
POR
OSCILLATOR
WATCHDOG
INTERNAL
SYSTEM
The embedded AVR core has five sources of reset:
•
•
•
•
•
During reset, all I/O registers except the MCU Status register are then set to their Initial Val-
ues, and the program starts execution from address $0000. The instruction placed in address
$0000 must be a JMP – absolute jump instruction to the reset handling routine. If the program
never enables an interrupt source, the interrupt vectors are not used, and regular program
code can be placed at these locations. The circuit diagram in Figure 35 shows the reset logic.
Table 15 defines the timing and electrical parameters of the reset circuitry.
CLOCK
TIMER
External Reset. The MCU is reset immediately when a low-level is present on the RESET
or AVR RESET pin.
Power-on Reset. The MCU is reset upon chip power-up and remains in reset until the
FPGA configuration has entered Idle mode.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
watchdog is enabled.
Software Reset. The MCU is reset when the SRST bit in the Software Control register is
set (one).
JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register,
one of the scan chains of the JTAG system. See “IEEE 1149.1 (JTAG) Boundary-scan” on
page 73.
MCU STATUS
DATA BUS
DELAY COUNTERS
JTAG RESET
REGISTER
SEL [4:0] CONTROLLED
BY FPGA CONFIGURATION
AT94K Series FPSLIC
FULL
S
R
Q
INTERNAL
RESET
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