AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 66

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Interrupt Response
Time
Sleep Modes
66
AT94K Series FPSLIC
• Bit 3 - ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1
value has been transferred to the input capture register – ICR1. ICF1 is cleared by the hard-
ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is
cleared by writing a logic 1 to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1
Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt
is executed.
• Bit 2 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data
in OCR2 – Output Compare Register 2. OCF2 is cleared by the hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic 1 to
the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable), and
the OCF2 are set (one), the Timer/Counter2 Output Compare Interrupt is executed.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic 1 to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00.
• Bit 0 - OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data
in OCR0 – Output Compare Register 0. OCF0 is cleared by the hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic 1 to
the flag. When the I-bit in SREG, and OCIE0 (Timer/Counter2 Compare Interrupt Enable), and
the OCF0 are set (one), the Timer/Counter0 Output Compare Interrupt is executed.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. Four clock cycles after the interrupt flag has been set, the program vector address for
the actual interrupt handling routine is executed. During this four clock-cycle period, the Pro-
gram Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is serviced.
A return from an interrupt handling routine (same as for a subroutine call routine) takes four
clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back
from the Stack, and the Stack Pointer is incremented by 2. When the AVR exits from an inter-
rupt, it will always return to the main program and execute one more instruction before any
pending interrupt is serviced.
To enter any of the three Sleep modes, the SE bit in MCUR must be set (one) and a SLEEP
instruction must be executed. The SM1 and SM0 bits in the MCUR register select which Sleep
mode (Idle, Power-down, or Power-save) will be activated by the SLEEP instruction, see
Table 11 on page 52.
In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA
interrupts, FPGA INT0...3, are triggered as low level-triggered interrupts. If an enabled inter-
rupt occurs while the MCU is in a Sleep mode, the MCU awakes, executes the interrupt
routine, and resumes execution from the instruction following SLEEP. The contents of the reg-
ister file, SRAM, and I/O memory are unaltered. If a reset occurs during Sleep mode, the MCU
wakes up and executes from the Reset vector
Rev. 1138F–FPSLI–06/02