m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 119

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Figure 1-40. Full E1 Interleaved Highway Frame
Figure 1-41
28529-DSH-001-K
(Continued)
(Continued)
(Continued)
IHRxInDo
IHRxSync
IHRxSync
IHRxData
IHRxData
IHRxInDo
is a block diagram showing how four serial links are combined.
16
A
0
A
16
B
B
0
Note: Only the transmt frame structure is shown, but the receive frame structure is identical
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0
C
C
NOTE:
NOTE:
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0
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D
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A
1
A
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B
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1
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B
The TC Processors belonging to the Interleaved Highway group should be configured in
xDSL mode, by setting PhyType to 110 in the Port Mode Control Registers (PMODE[2:0])
0x04, as this is required when using the Fractional T1/E1 logic. Also, the IOMODE registers
0x05 should be set to their default values. This is because the clock polarities in Interleaved
Highway mode are controlled via the TCCTRL registers. Also the Internal sync inputs to the
TC processor are tied low (inactive state when IOMODE[6] and IOMODE[4] are set to
default values in xDSL mode) so that they have no effect
The T1/E1 streams must be locked to the 8.192 MHz clock rate.
18
C
C
2
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D
2
D
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3
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A
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B
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C
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D
Mindspeed Proprietary and Confidential
Mindspeed Technologies
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4
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B
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4
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C
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D
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C
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D
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D
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B
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C
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D
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A
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C
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D
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A
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B
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C
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8
D
D
®
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B
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C
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D
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A
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B
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C
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D
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B
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C
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D
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A
12
Functional Description
B
28
B
12
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C
C
12
28
D
D
13
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A
A
13
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B
B
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C
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D
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D
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A
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A
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30
B
B
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C
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C
14
30
D
A
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A
15
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B
B
15
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C
C
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D
D
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