m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 172

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.10
The UTOP1 register controls the UTOPIA resets.
2.2.11
The UTOP2 register contains the multi-PHY address value for the port.
28529-DSH-001-K
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
(2) The default for these bits is the port number for each port. (0000—Port 0, 0001—Port 1, 0010—Port 2, 0011—Port 3, 0100—Port 4,
Bit
Bit
7
6
5
4
3
2
1
0
0101—Port 5, 0110—Port 6, 0111—Port 7, 1000—Port 8, 1001—Port 9, 1010—Port 10, 1011—Port 11, 1100—Port 12, 1101—Port
13, 1110—Port 14, 1111—Port 15, 0000—Port 16, 0001—Port 17, 0010—Port 18, 0011—Port 19, 0100—Port 20, 0101—Port 21,
0110—Port 22, 0111—Port 23, 1000—Port 24, 1001—Port 25, 1010—Port 26, 1011—Port 27, 1100—Port 28, 1101—Port 29,
1110—Port 30, 1111—Port 31)
7
6
5
4
3
2
1
0
Default
Default
(2)
(2)
(2)
(2)
0
0
1
0
0
0
0
0
0
0
0
0
0x0D—UTOP1 (UTOPIA Control Register 1)
0x0E—UTOP2 (UTOPIA Control Register 2) (TC Block)
TxReset
RxReset
UtopDis
MphyAddr[4]—MSB
MphyAddr[3]
MphyAddr[2]
MphyAddr[1]
MphyAddr[0]—LSB
(1)
Name
Name
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When written to a logical 1, this bit resets the transmit FIFO pointers. This reset should only be
used as a test function because it can create short cells.
When written to a logical 1, this bit resets the receive FIFO pointers. This reset should only be
used as a test function because it can create short cells.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
When written to a logical 1, this bit disables UTOPIA outputs for this port.
These bits are the Multi-PHY Device Address. Each M2852x port should have a unique address.
These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the bit values,
the port is accessed. This port ignores any transactions meant for another port or PHY device.
®
Description
Description
Registers
157