m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 89

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

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Table 1-22
Table 1-22.
As an example, setting IMA_SysClk = 49.152 MHz constrains the Maximum Aggregate BW to be less than 152.9
Mbps for configurations with at least 1 IMA group. For a 32 port application, depending on the number of active IMA
groups, this implies a maximum aggregate BW in the range of 109.2 - 152.9 Mbps with an average link BW in the
range of 3.41 - 4.78 Mbps.
As another example, for a 16 port application, with 16 IMA groups, the average link BW would be limited to 8.192
Mbps (131.1 Mbps / 16). This average link rate would increase if less than 16 IMA groups were active.
1.12.2.2
IMA_SysClk is also used to sample the serial receive clocks (SPRxClk) and IMA_RefClk. These sampled signals
are used for IMA frame rate generation. When operating with the Interleaved Highway interface enabled, the 4x
input clock (IHRxClk) is first divided by 4 before being distributed to the IMA block where it is sampled. If the serial
interface is operating in fractional T1/E1 mode, either directly or using the Interleaved Highway interface, the
resulting “gated” clock being routed over to the IMA core is not used.
The requirements of the SPRxClk, IHRxClk, and IMA_RefClk inputs are summarized below:
28529-DSH-001-K
1 IMA group
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If only pass-throughs are enabled, then the aggregate cell bandwidth limitation is:
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IMA_SysClk
49.152 MHz
66 MHz
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (28 / 9).
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (16 / 5)
list some examples.
Maximum Aggregate Bandwidth Examples
Serial Clock Sampling
# ports
1-32
1-32
1-32
1-32
1-32
1-32
1-32
1-32
# groups
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Mindspeed Technologies
≤ 16
≤ 32
≤ 16
≤ 32
0
1
0
1
Maximum BW (Mbps)
157.3
152.9
131.1
109.2
211.2
205.3
176.0
146.7
®
Functional Description
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