m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 175

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.16
The TXHDR4 register contains the fourth byte of the Transmit Cell Header. (See 0x10—TXHDR1.)
2.2.17
The TXIDL1 register contains the first byte of the Transmit Idle Cell Header. It controls the header value that is
inserted in the transmitted idle cells. This header consists of 32 bits divided among four registers.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x13—TXHDR4 (Transmit Cell Header Control Register 4)
0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1)
TxHdr4[7]
TxHdr4[6]
TxHdr4[5]
TxHdr4[4]
TxHdr4[3]
TxHdr4[2]
TxHdr4[1]
TxHdr4[0]
TxIdl1[7]
TxIdl1[6]
TxIdl1[5]
TxIdl1[4]
TxIdl1[3]
TxIdl1[2]
TxIdl1[1]
TxIdl1[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
These bits hold the Transmit Header values for Octet 4 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell.
VCI bits
Payload-type bits
GFC/VPI bits
(for UNI they are GFC bits, for NNI the are VPI bits)
VPI bits
Cell Loss Priority bit
®
Description
Description
Registers
160