m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 185

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.36
The IDLMSK4 register contains the fourth byte of the Receive Idle Cell Mask. (See 0x24—RXMSKL1.)
2.2.37
The ENCELLT register controls which of the interrupts listed in the TxCellInt register (0x2C) appear on the
MicroInt* pin (pin AA1), provided that both EnTxCellInt (bit 1) in the ENSUMINT register (0x01) and EnPortInt bit in
the appropriate ENSUMPORTn (n= 0 - 3) register (0xF06, 0xF08, 0xF0A or 0xF0C) for this port are enabled, and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4)
0x28—ENCELLT (Transmit Cell Interrupt Control Register)
IdlMsk4[7]
IdlMsk4[6]
IdlMsk4[5]
IdlMsk4[4]
IdlMsk4[3]
IdlMsk4[2]
IdlMsk4[1]
IdlMsk4[0]
EnParErrInt
EnSOCErrInt
EnTxOvflInt
EnRxOvflInt
EnCellSentInt
Name
Name
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
These bits hold the Receive Idle cell header mask for Octet 4 of the incoming cell.
When written to a logical 1, this bit enables the Parity Error Interrupt.
When written to a logical 1, this bit enables the Start of Cell Error Interrupt.
When written to a logical 1, this bit enables the Transmit FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Cell Sent Interrupt.
Reserved for factory test, ignore.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
®
Description
Description
Registers
170