m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 188

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.42
The RXCELL register contains status for the cell receiver. This register is cleared on read.
2.2.43
The IDLCNTL counter tracks the number of received idle cells. This byte of the counter should be read first. The
counter is cleared on read.
28529-DSH-001-K
Footnote:
(1) This status indicates an event that occurred since the register was last read.
(2) This status reflects the current state of the circuit.
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x2F—RXCELL (Receive Cell Status Register)
0x30—IDLCNTL (Idle Cell Receive Counter [Low Byte])
LOCD
HECDet
HECCorr
CellRcvd
IdleRcvd
NonMatch
NonZerGFC
IdleCnt[7]
IdleCnt[6]
IdleCnt[5]
IdleCnt[4]
IdleCnt[3]
IdleCnt[2]
IdleCnt[1]
IdleCnt[0]
(2)
(1)
(1)
(1)
Name
Name
(1)
—
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When a logical 1 is read, this bit indicates a Loss of Cell Delineation.
When a logical 1 is read, this bit indicates that an uncorrected HEC Error was detected.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
Reserved, ignore this bit.
When logical 1 is read, this bit indicates that a valid cell was received.
When a logical 1 is read, this bit indicates that a cell with a header matching the receive idle cell
header value and mask criteria was received.
When a logical 1 is read, this bit indicates that a cell has been rejected by the cell screening
function.
When a logical 1 is read, this bit indicates that a cell with a Non-zero GFC field in the header was
received.
Received cell counter bit 7.
Received cell counter bit 6.
Received cell counter bit 5.
Received cell counter bit 4.
Received cell counter bit 3.
Received cell counter bit 2.
Received cell counter bit 1.
Received cell counter bit 0 (LSB).
®
Description
Description
Registers
173