m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 203

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.3.21
2.3.22
2.3.23
28529-DSH-001-K
Bit
Bit
Bit
7-1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0000000
Default
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF16—TCCTRL6 (TC Control Register for TC ports 24-27)
0xF17—TCCTRL7 (TC Control Register for TC ports 28-31)
0xF18—ONESECINT (One Second Interrupt Status Register)
IhTxDatShft6
IhTxClkPol6
IhRxClkPol6
EnIH6
EnFrac[27]
EnFrac[26]
EnFrac[25]
EnFrac[24]
IhTxDatShft7
IhTxClkPol7
IhRxClkPol7
EnIH7
EnFrac[31]
EnFrac[30]
EnFrac[29]
EnFrac[28]
OneSecInt
Name
Name
Name
-
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When set to 1, the Tx data on the Interleaved Highway Data Bus 6 will be output 1/2 IHTxClk6
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 6 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk6, set to 1 for
falling edge.
Interleaved Highway Bus 6 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk6, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 24-27.
When set, this bit enables fractional T1/E1 logic for TC port 27.
When set, this bit enables fractional T1/E1 logic for TC port 26.
When set, this bit enables fractional T1/E1 logic for TC port 25.
When set, this bit enables fractional T1/E1 logic for TC port 24.
When set to 1, the Tx data on the Interleaved Highway Data Bus 7 will be output 1/2 IHTxClk7
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 7 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk7, set to 1 for
falling edge.
Interleaved Highway Bus 7 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk7, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 28-31.
When set, this bit enables fractional T1/E1 logic for TC port 31.
When set, this bit enables fractional T1/E1 logic for TC port 30.
When set, this bit enables fractional T1/E1 logic for TC port 29.
When set, this bit enables fractional T1/E1 logic for TC port 28.
Reserved, set to zero
This bit is the indicator of the one second interrupt
®
Description
Description
Description
Registers
188