m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 215

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.4.23
This register is used in conjunction with 0x816 to configure the operation of the DSL Clock Generator in the IMA
core. Register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected
using register 0x816 and the configuration for that element is programmed using register 0x817.
28529-DSH-001-K
3–0
7–0
7–0
7–0
Bit
7-0
7-6
5-4
3-1
7
6
5
4
0
Default
0x00
0x00
0x00
0x00
—
—
—
—
0
0
0
0
0
0x817—IMA_DSL_CLOCK_GEN_DATA (IMA_DSL Clock Generator Data)
EnRxSyn
DSLClkGen
IMA_ClkSel
Pre-scaler Terminal
Count
Pre-scaler Numerator
Reference Clock Divisor This field contains 8 of the 9 bits of the terminal count for the reference clock divisor. The
Group Clock Multiplier
Factor (lsbs)
Rate Multiplier
Group Clock Multiplier
Factor (msb)
Name
—
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved. Set to 0.
Enable Rx Timing Synthesizers
Substitute DSL clock generator
0 = Use IMA_SysClk as input to DSL Clock Generators
1 = Use IMA_RefClk as input to DSL Clock Generators
Reserved. Set to 0.
This field contains the terminal count of the pre-scaler clock divider. The pre-scaler denominator
is the value of this field plus 1.
This field contains the numerator for the pre-scaler.
reference clock divisor counts from 0 to the terminal count which is given by the value of this
field plus 257. As an example if the value of this register is 63 decimal, then the reference clock
divisor will be 320.
This register contains the 8 lsbs of the payload bandwidth for the ports used in the IMA group.
The contents of this register are multiplied by 8kbps and the Rate Multiplier in order to obtain
the bandwidth.
Reserved. Set to 0.
Scale factor used to generate link rates > Intermediate Frequency
Reserved. Set to 0.
This register contains the msb of the payload bandwidth for the ports used in the IMA group.
The contents of this register are multiplied by 2048kbps and the Rate Multiplier in order to
obtain the bandwidth.
For Control Type = 1/Sub-type = 0
0 = Use SPRxClk inputs
1 = Use synthesizers instead of SPRxClk inputs
0 = Use IMA_SysClk/24 in IMA group clock and Tx_TRL selectors
1 = Use DSL Clock generator outputs when Timing Source is set to 0x20 in register
0x811.
0 = Multiply rate by 1 (typically used by link rates < 3.072 Mbps)
1 = Multiply rate by 2 (typically used by 3.072 < link rates < 6.144 Mbps)
2 = Multiply rate by 4 (typically used by link rates > 6.144 Mbps)
3 = Not defined.
For Control Type = 1/Sub-type = 1
For Control Type = 1/Sub-type = 2
For Control Type = 2, 4
For Control Type = 3, 5
For Control Type = 0
®
Description
Registers
200