m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 173
m28529-12
Manufacturer Part Number
m28529-12
Description
Inverse Multiplexing For Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529-12.pdf
(309 pages)
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2.2.12
The contents of the UDF2 register are inserted into the UDF2 byte on the UTOPIA receive bus when operating in
16-bit UTOPIA mode.
2.2.13
The TXHDR1 register contains the first byte of the Transmit Cell Header. It controls the header value that is
inserted in the transmitted cell. This header consists of 32 bits divided among four registers (TXHDR1–4).
28529-DSH-001-K
Footnote:
(1) The default for these bits is the port number for each port. (0000—Port 0, 0001—Port 1, 0010—Port 2, 0011—Port 3, 0100—Port 4,
Bit
Bit
0101—Port 5, 0110—Port 6, 0111—Port 7, 1000—Port 8, 1001—Port 9, 1010—Port 10, 1011—Port 11, 1100—Port 12, 1101—Port
13, 1110—Port 14, 1111—Port 15, 0000—Port 16, 0001—Port 17, 0010—Port 18, 0011—Port 19, 0100—Port 20, 0101—Port 21,
0110—Port 22, 0111—Port 23, 1000—Port 24, 1001—Port 25, 1010—Port 26, 1011—Port 27, 1100—Port 28, 1101—Port 29,
1110—Port 30, 1111—Port 31)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
(1)
(1)
(1)
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0x0F—UDF2 (UDF2 Control Register)
0x10—TXHDR1 (Transmit Cell Header Control Register 1)
UDF2[7]
UDF2[6]
UDF2[5]
UDF2[4]
UDF2[3]
UDF2[2]
UDF2[1]
UDF2[0]
TxHdr1[7]
TxHdr1[6]
TxHdr1[5]
TxHdr1[4]
TxHdr1[3]
TxHdr1[2]
TxHdr1[1]
TxHdr1[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
The contents of this register are output over the UTOPIA receive bus when operating in UTOPIA
16-bit mode. The default matches the port address.
These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
GFC/VPI bits
(for UNI they are GFC bits, for NNI they are VPI bits)
VPI bits
®
Description
Description
Registers
158
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