m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 171

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.2.8
The ERRPAT register provides the error pattern for the HEC error insertion function. ErrHEC (bit 4) in the CGEN
register (0x08) enables this function. Each bit in the error pattern register is XORed with the corresponding bit of
the calculated HEC byte to be errored.
2.2.9
The CVAL register controls the validation of incoming cells.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0x0B—ERRPAT (Error Pattern Control Register)
0x0C—CVAL (Cell Validation Control Register)
ErrPat[7]
ErrPat[6]
ErrPat[5]
ErrPat[4]
ErrPat[3]
ErrPat[2]
ErrPat[1]
ErrPat[0]
RejHdr
DelIdle
EnRxCos
EnRxCellScr
EnHECCorr
DisHECChk
DisCellRcvr
DisLOCD
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Error pattern bit 7.
Error pattern bit 6.
Error pattern bit 5.
Error pattern bit 4.
Error pattern bit 3.
Error pattern bit 2.
Error pattern bit 1.
Error pattern bit 0.
When written to a logical 1, this bit enables the Rejection of certain Header cells. When enabled,
cells with headers matching the RXHDRx/RXMSKx definition are rejected and all others are
accepted. When written to a logical 0, cells with matching headers are accepted and cells with
non-matching headers are rejected.
When written to a logical 1, this bit enables the Deletion of Idle Cells. When enabled, cells
matching the RXIDL/IDLMSK definition are deleted from the received cell stream. When written
to a logical 0, idle cells are included in the received stream.
When written to a logical 1, this bit enables the Receive HEC Coset. When written to a logical 0,
the HEC Coset is disabled.
When written to a logical 1, this bit enables the Receive Cell Scrambler. When written to a logical
0, the Receive Cell Scrambler is disabled.
When written to a logical 1, this bit enables HEC Correction. When written to a logical 0, HEC
Correction is disabled.
When written to a logical 1, this bit disables HEC Checking. When written to a logical 0, HEC
checking is performed as a cell validation criterion. See
When written to a logical 1, this bit disables the Cell Receiver. When disabled, all cell reception is
disabled on the next cell boundary. When written to a logical 0, cell reception begins or resumes
on the next cell boundary.
When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are
passed even if cell delineation has not been found. When written to a logical 0, cells are passed
only while cell alignment has been achieved. See
®
Description
Description
Table
1-26.
Table
1-26.
Registers
156