m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 297

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Table 4-4.
Table 4-5.
Table 4-6.
28529-DSH-001-K
Comments:
Comments:
IDC.10
IDC.11
IDC.12
IDC.13
LDD.1
LDD.2
LDD.3
IDC.6
IDC.7
IDC.8
IDC.9
Item
Item
Item
IIO.1
IIO.2
IIO.3
Does the implementation indicate the selected or changed TRL to the FE over
the “Transmit Timing Information” field in the ICP cell?
Does the implementation derive the Tx IDCC from the selected TRL
according to Equation 1 on page 40?
When running in the CTC mode, does the implementation introduce a stuff
event every 2048 ICP, Filler and ATM layer cells on all links?
Does the implementation introduce a stuff event every 2048 ICP, Filler and
ATM layer cells on the TRL?
Does the implementation introduce stuff events on links other than the TRL
in order to compensate for the timing difference between the TRL and the
other links?
Does the implementation remove CDV attributed to the presence of ICP cells
by a mechanism equivalent to providing a small smoothing buffer into which
cells are placed after reordering and after removing ICP cells?
If the TRL is in the Working state and the FE has, for at least 100
milliseconds, identified a given link as the TRL, does the implementation
derive the Rx IDCR using the incoming link indicated by the FE as the TRL?
Does the implementation have an equivalent behavior to the following: when
the IMA data cell clock at the receiver ticks, one cell is removed from the
smoothing buffer; if the cell is a Filler cell, then the Filler cell is discarded and
nothing passed to the ATM layer; if the cell is not a Filler cell, then it is passed
to the ATM layer?
53?
IMA unit via the ICP cells?
Does the implementation introduce a differential delay among the
constituent links of a maximum of 2.5 cell times at the physical link rate?
Does the implementation tolerate up to at least 25 milliseconds of link
differential delay on receive?
Does the implementation allow configuring the link differential delay
tolerance?
Does the implementation support the Tx LSM defined in Table 8 on page 52?
Does the implementation support the Rx LSM defined in Table 9 on page
Does the implementation signal the current state of the Tx LSM to the FE
IMA Data Cell (IDC) Rate Implementation Functions (2 of 2)
Link Differential Delay (LDD) Functions
IMA Interface Operation (IIO) Functions (1 of 4)
Protocol feature
Protocol feature
Protocol feature
Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
(O-9)
(O-9)
Cond. for
Cond. for
Cond. for
Status
Status
Status
Status
Status
Status
Pred.
Pred.
Pred.
M
M
M
M
M
M
M
M
M
M
M
M
M
O
(R-74)
(R-75)
(O-13)
(R-76)
(R-77)
(R-78)
(R-68)
(R-69)
(R-70)
(CR-5)
(CR-6)
(R-71)
(R-72)
(R-73)
Ref.
Ref.
Ref.
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Appendices
Support
Support
Support
282