m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 54

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Figure 1-9.
28529-DSH-001-K
Address Strobe, Write Control I
PHY Transmit Address Bus O
PHY Receive Address Bus O
ATM Transmit Address Bus I
ATM Receive Address Bus I
Write/Read Read Control I
Sync/Async Mode Select I
External Memory Select I
PHY Transmit Enable O
PHY Receive Enable O
ATM Transmit Enable I
IMA Reference Clock I
PHY Transmit Clock O
Microprocessor Clock I
PHY Interface Select I
ATM Receive Enable I
ATM Transmit Clock I
PHY Receive Clock O
Memory Data Bus I/O
M28529 Logic Diagram (UTOPIA-to-UTOPIA)
ATM Receive Clock I
IMA System Clock I
Test Mode Select I
Test Data Input I
8kHzIn Clock I
Address Bus I
Test Enable I
Chip Select I
Test Mode I
Test Reset I
Test Clock I
Reset I
MCS
MAS*, MWr
MicroAddr[11:0]
atmUTxAddr[4:0]
phyURxAddr[4:0]
PhyIntFcSel
MW/R, MRd
TRST
TestEnable
atmURxENB[1:0]
atmURxAddr[4:0]
ExtMemSel
phyUTxClk
phyUTxEnb[1:0]*
phyUTxAddr[4:0]
phyURxClk
phyURxEnb[1:0]*
MSyncMode
MicroClk
TMS
TDI
TestMode
atmUTxCLK
atmUTxENB[1:0]
atmURxCLK
IMA_SysClk
TCK
IMA_RefClk
8kHzin*
MemData[15:0]
Reset*
Mindspeed Proprietary and Confidential
Mindspeed Technologies
*
*
(1)
*
*
*
PHY UTOPIA Transmit
PHY UTOPIA Receive
ATM UTOPIA Transmit
ATM UTOPIA Receive
Microprocessor
JTAG Interface
One Second
External Memory
Reset
Interface
Interface
Interface
Interface
IMA Clocks
Interface
Interfac e
Interface
(1)
Pulled High
atmUTxData[15:0]
atmURxData[15:0]
phyURxData[15:0]
®
phyUTxData[15:0]
atmURxClAv[1:0]
MemCtrl_ADSC*
phyUTxClAv[1:0]
atmUTxClAv[1:0]
phyURxClAv[1:0]
MemAddr[19:0]
MicroData[7:0]
MemCtrl_WE
MemCtrl_CE
MemCtrl_OE
MemCtrl_Clk
atmUTxSOC
phyURxSOC
atmURxSOC
phyUTxSOC
StatOut [1:0]
atmURxPrty
phyURxPrty
atmUTxPrty
TxTRL[1:0]
phyUTxPrty
OneSecIO
MicroInt
MRdy
TDO
*
*
*
*
O PHY Transmit Start of Cell
O PHY Transmit Data Bus
O PHY Transmit Parity
I PHY Receive Cell Available
I PHY Receive Start of Cell
I PHY Receive Data Bus
I PHY Receive Parity
O Test Data Output
O ATM Receive Cell Available
O ATM Receive Start Of Cell
O ATM Receive Parity
O ATM Receive Data Bus
O Transmit Reference Clock
O Memory Address Bus
O Chip Enable
O Output Enable
O Write Enable
O SRAM Clock
O Address Enable
O Summary Interrupt
I PHY Transmit Cell Available
O Status Output
O Ready
I/O One Second Input/Output
I/O Microprocessor Data Bus
O ATM Transmit Cell Available
I ATM Transmit Start Of Cell
I ATM Transmit Parity
I ATM Transmit Data Bus
Functional Description
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