m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 81

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

1.7
Source loopback checks that the host (the ATM layer) is communicating with the PHY. It is enabled and disabled in
bit 5 of the PMODE register (0x04). When source loopback is enabled for a given port, all data transmitted by the
M2852x on that port is also looped back through the Receive Line Interface. Data from the framer interface is
ignored.
There are two different modes of source loopback, source loopback mode 0 and source loopback mode 1. The
loopbacks work in TC enabled modes.
1.7.1
During source loopback mode 0, the port is automatically placed in General Purpose mode and an internal clock
(IMA_SysClk/2 for IMA mode, atmUTxClk for TC Only mode) is used as the clock to loop back cells. As a result of
the automatic mode switch and clock used, the data on the Tx serial lines will be corrupted.
1.7.2
During source loopback mode 1, the port is not placed in General Purpose mode (the serial framing remains as
configured) and the SPTxCLK and SPTxSync device input signals are routed along with the SPTxDATA to the TC
receive port circuit.
Figure 1-12. Source Loopback Diagram (For simplicity the diagram shows the TC Block Only.)
28529-DSH-001-K
SPTxSync
SPTxData
* See Note
SPTxClk
Interface
Framer
(Line)
Source Loopbacks (UTOPIA-to-Serial Configuration Only)
Source Loopback Mode 0
Source Loopback Mode 1
* SPTxData will be corrupted in in Source Loopback mode 0
This segment is replicated for ports 0-31
Loopback
Control
TC Transmit Port
TC Receive Port
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Mindspeed Technologies
Alignment
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
®
4-cell
FIFO
4-cell
FIFO
Interface
Transmit
UTOPIA
Interface
UTOPIA
Receive
Level 2
Level 2
Host
Host
Functional Description
Interface
UTOPIA
Level 2
atmURxSOC
atmURxData[15:0]
atmURxPrty
atmUTxEnb*
atmUTxSOC
atmUTxData[15:0]
atmUTxPrty
atmUTxAddr[4:0]
atmURxClAv
atmURxEnb*
atmURxAddr[4:0]
atmUTxClAv
atmURxClk
atmUTxClk
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