m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 61

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Table 1-11.
28529-DSH-001-K
phyURxData[0]
phyURxData[1]
phyURxData[2]
phyURxData[3]
phyURxData[4]
phyURxData[5]
phyURxData[6]
phyURxData[7]
phyURxData[8]
phyURxData[9]
phyURxData[10]
phyURxData[11]
phyURxData[12]
phyURxData[13]
phyURxData[14]
phyURxData[15]
phyURxSOC
phyURxPrty
phyUTxAddr[0]
phyUTxAddr[1]
phyUTxAddr[2]
phyUTxAddr[3]
phyUTxAddr[4]
phyUTxClAv[0]
phyUTxClAv[1]
phyUTxClk
Pin Label
M2852x Pin Descriptions (6 of 18)
PHY UTOPIA Receive
Data
PHY UTOPIA Start of Cell
PHY UTOPIA Receive
Parity
PHY UTOPIA Transmit
Address
PHY UTOPIA Transmit
Cell Available
PHY UTOPIA Transmit
Clock
Signal Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
AB14
AC15
AD14
AC14
AD13
AC13
AD12
AC12
AD17
AE14
AF15
AF14
AF13
AE13
AF12
AE12
AF11
AE18
No.
G2
G3
H4
D1
G4
F1
F2
E2
I/PD
I/PD
I/PD
I/PD
I/O
O
O
Transmit PHY Cell Bus address. The following limitations apply:
Received 16 bit PHY Cell Data. All received cells are passed to the
internal IMA processor.
Start of Cell synchronization signal for Receive PHY cells (active
high). Indicates that the first byte of the cell is being placed on the
PhyURxData[7:0] bus.
Odd parity calculated over phyURxData[15:0] pins in 16-bit mode
and over phyURxData[7:0] pins in 8-bit mode.
Cell Available signals for Transmit ATM cells. When phyUTxClAv[n]
is active high, the PHY has space available for one or more
complete cells. To support different PHY devices, separate cell
available signals are provided.
IMA_SysClk divided by two.
M28525
M28529
®
Device
Description
Functional Description
Addresses
0–15, 31
0–31
46