m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 176
m28529-12
Manufacturer Part Number
m28529-12
Description
Inverse Multiplexing For Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529-12.pdf
(309 pages)
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2.2.18
The TXIDL2 register contains the second byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
2.2.19
The TXIDL3 register contains the third byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2)
0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3)
TxIdl2[7]
TxIdl2[6]
TxIdl2[5]
TxIdl2[4]
TxIdl2[3]
TxIdl2[2]
TxIdl2[1]
TxIdl2[0]
TxIdl3[7]
TxIdl3[6]
TxIdl3[5]
TxIdl3[4]
TxIdl3[3]
TxIdl3[2]
TxIdl3[1]
TxIdl3[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell.
These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell.
VPI bits
VCI bits
VCI bits
®
Description
Description
Registers
161
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