h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1001

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h8s-2635

Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
22B.1 Overview
The chip has a built-in clock pulse generator (CPG) that generates the system clock ( ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, system clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, and subclock
divider. The frequency can be changed by means of the PLL circuit in the CPG. Frequency
changes are performed by software by means of settings in the system clock control register
(SCKCR) and low-power control register (LPWRCR).
22B.1.1 Block Diagram
Figure 22B-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Legend:
LPWRCR:
SCKCR:
Low-power control register
System clock control register
divider (1/128)
oscillator
Clock
Subclock
(H8S/2639 Group, H8S/2635 Group)
Figure 22B-1 Block Diagram of Clock Pulse Generator
Section 22B Clock Pulse Generator
Section 22B Clock Pulse Generator (H8S/2639 Group, H8S/2635 Group)
(×1, ×2, ×4)
PLL circuit
LPWRCR
WDT1 count clock
STC1, STC0
φSUB
selection
System
circuit
clock
System clock
to φ pin
Rev. 6.00 Feb 22, 2005 page 941 of 1484
clock divider
Medium-
speed
supporting modules
Internal clock to
φ/2 to
φ/32
φ
selection
SCKCR
master
circuit
clock
Bus
REJ09B0103-0600
Bus master clock
to CPU and DTC
SCK2 to SCK0

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