h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 205

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
(1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
(2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
(3) When the SLEEP instruction causes a transition from subactive mode * to high-speed
(4) When the SLEEP instruction causes a transition to software standby mode or watch mode * :
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
sleep mode, or from subactive mode * to subsleep mode * :
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode * , and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2
(A)).
subactive mode * :
After execution of the SLEEP instruction, a transition is made to subactive mode * via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).
(medium-speed) mode:
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition exception
handling. After the transition, PC break interrupt handling is executed, then the instruction at
the address after the SLEEP instruction is executed (figure 6-2 (C)).
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2
(D)).
U-mask and W-mask versions only.
Operation in Transitions to Power-Down Modes
Rev. 6.00 Feb 22, 2005 page 145 of 1484
Section 6 PC Break Controller (PBC)
REJ09B0103-0600