h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 653

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Does not meet the I
Item
t
SDAHO
Note on ICDR Read at End of Master Reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 15-18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
t
Indication
3 t
cyc
2. Calculated using the I
cyc
Section 15 I
following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the
rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the
transfer rate; (d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions.
speed mode: 1300 ns min.).
Standard
mode
High-speed
mode
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
t
Influence
(Max.)
0
0
Sr
2
C bus interface specification. Remedial action such as the
/t
2
Sf
C bus specification values (standard mode: 4700 ns min.; high-
Time Indication (at Maximum Transfer Rate) [ns]
I
Specifi-
cation
(Min.)
0
0
2
C Bus
5 MHz
600
600
=
Rev. 6.00 Feb 22, 2005 page 593 of 1484
8 MHz
375
375
=
2
C bus interface specifications are
300
300
10 MHz
=
REJ09B0103-0600
16 MHz
188
188
=
20 MHz
150
150
=