h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 153

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

4.1
4.1.1
As table 4-1 indicates, exception handling may be caused by a reset, direct transition * , trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
Table 4-1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used
with the other versions.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
4. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in
Overview
Exception Handling Types and Priority
Exception Type
Reset
Trace *
Direct transition *
Interrupt
Trap instruction (TRAPA) *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot
be used with the other versions.
Supported by the H8S/2635.
Exception Types and Priority
1
Section 4 Exception Handling
4
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the
pin, or when the watchdog overflows. The CPU enters the
reset state when the
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when a direct transition occurs due to execution of a
SLEEP instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued *
Started by execution of a trap instruction (TRAPA)
Rev. 6.00 Feb 22, 2005 page 93 of 1484
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pin is low.
Section 4 Exception Handling
REJ09B0103-0600
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2