h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 494

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 Watchdog Timer
12.5.2
If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before changing the value of bits PSS * and CKS2 to CKS0.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
12.5.3
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4
The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, but TCNT and TSCR of the WDT are reset.
12.5.5
If conflict occurs between OVF flag clearing and OVF flag reading in interval timer mode, the
flag may not be cleared by writing 0 to OVF even though the OVF = 1 state has been read. When
interval timer interrupts are disabled and the OVF flag is polled, for instance, and there is a
possibility of conflict between OVF flag setting and reading, the OVF = 1 state should be read at
least twice before writing 0 to OVF in order to clear the flag.
Rev. 6.00 Feb 22, 2005 page 434 of 1484
REJ09B0103-0600
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
Changing Value of PSS* and CKS2 to CKS0
Switching between Watchdog Timer Mode and Interval Timer Mode
Internal Reset in Watchdog Timer Mode
OVF Flag Clearing in Interval Timer Mode