h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 636

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 I
[14] If the IRTR flag value is 0, clear the IRIC flag to 0 to cancel the wait state. Return to reading
[15] Clear the WAIT bit in ICMR to 0 to cancel the wait mode. Then clear the IRIC flag to 0. The
[16] Read the final receive data in ICDR.
[17] Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
Rev. 6.00 Feb 22, 2005 page 576 of 1484
REJ09B0103-0600
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
Master transmit mode
receive operation has finished, perform the issue stop condition processing described in step
[15] below.
the IRIC flag, as described in step [12], to detect the end of the receive operation.
IRIC flag should be cleared when the value of WAIT is 0 (The stop condition may not be
output properly when the issue stop condition instruction is executed if the WAIT bit was
cleared to 0 after the IRIC flag is cleared to 0).
and generates the stop condition.
2
Figure 15-12 Example of Master Receive Mode Operation Timing
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
A
9
[1] TRS cleared to 0
IRIC clearance
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
[2] ICDR read (dummy read)
Master receive mode
1
2
(MLS = ACKB = 0, WAIT = 1)
3
Data 1
4
5
Bit 2 Bit 1 Bit 0
6
7
[6] IRIC clearance
8
(cancel wait)
[4] IRTR = 0
[3]
A
[3]
[4] IRTR = 1
9
[5] ICDR read
(data 1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Data 1
1
2
Data 2
[6] IRIC clearance
3
4
5