MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 135

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.3.2.1 Power-On Reset
MC68HC908AP Family — Rev. 2.5
MOTOROLA
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
IRST
ICLK
RST
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A POR pulse is generated.
The pin is driven low during the oscillator stabilization time.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096
ICLK cycles to allow stabilization of the oscillator.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
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ILLEGAL ADDRESS RST
Figure 9-6. Sources of Internal Reset
RST PULLED LOW BY MCU
ILLEGAL OPCODE RST
Figure 9-5. Internal Reset Timing
32 CYCLES
COPRST
POR
LVI
32 CYCLES
INTERNAL RESET
System Integration Module (SIM)
Reset and System Initialization
VECTOR HIGH
Data Sheet
135