MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 260

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Infrared Serial Communications
14.6.2.5 Transmitter Interrupts
14.6.3 Receiver
14.6.3.1 Character Length
Data Sheet
260
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the
IRSCDR to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit
becomes set and just before writing the next byte to the IRSCDR.
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
Figure 14-8
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in IRSCI control register 1 (IRSCC1) determines character length.
When receiving 9-bit data, bit R8 in IRSCI control register 2 (IRSCC2) is
the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the
eighth bit (bit 7).
Freescale Semiconductor, Inc.
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For More Information On This Product,
SCI transmitter empty (SCTE) — The SCTE bit in IRSCS1
indicates that the IRSCDR has transferred a character to the
transmit shift register. SCTE can generate a transmitter CPU
interrupt request. Setting the SCI transmit interrupt enable bit,
SCTIE, in IRSCC2 enables the SCTE bit to generate transmitter
CPU interrupt requests.
Transmission complete (TC) — The TC bit in IRSCS1 indicates
that the transmit shift register and the IRSCDR are empty and that
no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in IRSCC2 enables the TC bit
to generate transmitter CPU interrupt requests.
Go to: www.freescale.com
shows the structure of the SCI receiver.
MC68HC908AP Family — Rev. 2.5
MOTOROLA