MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 160

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Monitor ROM (MON)
10.3.2 Data Format
10.3.3 Break Signal
10.3.4 Baud Rate
Data Sheet
160
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
The communication baud rate is controlled by the crystal frequency and
the state of the PTB0 pin (when IRQ1 is set to V
monitor mode. When PTB0 is high, the divide by ratio is 1024. If the
PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio
is 512.
If monitor mode was entered with V
is set at 1024, regardless of PTB0. If monitor mode was entered with V
on IRQ1, then the internal PLL steps up the external frequency,
presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions
for monitor mode entry require that the reset vector is blank.
START
Freescale Semiconductor, Inc.
BIT
For More Information On This Product,
0
BIT 0
1
Go to: www.freescale.com
2
MISSING STOP BIT
BIT 1
3
Figure 10-3. Monitor Data Format
Figure 10-4. Break Transaction
4
BIT 2
5
6
BIT 3
7
BIT 4
DD
BIT 5
on IRQ1, then the divide by ratio
2-STOP BIT DELAY BEFORE ZERO ECHO
MC68HC908AP Family — Rev. 2.5
BIT 6
0
1
TST
BIT 7
2
) upon entry into
3
STOP
BIT
4
5
START
MOTOROLA
NEXT
BIT
6
7
SS