MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 268

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MC68HC908AP16CFA

Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Infrared Serial Communications
14.6.3.7 Receiver Interrupts
14.6.3.8 Error Interrupts
Data Sheet
268
The following sources can generate CPU interrupt requests from the SCI
receiver:
The following receiver error flags in IRSCS1 can generate CPU interrupt
requests:
Freescale Semiconductor, Inc.
For More Information On This Product,
SCI receiver full (SCRF) — The SCRF bit in IRSCS1 indicates that
the receive shift register has transferred a character to the
IRSCDR. SCRF can generate a receiver interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in IRSCC2 enables
the SCRF bit to generate receiver CPU interrupts.
Idle input (IDLE) — The IDLE bit in IRSCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the RxD pin. The idle line
interrupt enable bit, ILIE, in IRSCC2 enables the IDLE bit to
generate CPU interrupt requests.
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the IRSCDR. The previous character
remains in the IRSCDR, and the new character is lost. The
overrun interrupt enable bit, ORIE, in IRSCC3 enables OR to
generate SCI error CPU interrupt requests.
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in IRSCC3 enables
NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in IRSCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in IRSCC3 enables FE to generate SCI
error CPU interrupt requests.
Parity error (PE) — The PE bit in IRSCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in IRSCC3 enables PE to generate SCI error
CPU interrupt requests.
Go to: www.freescale.com
MC68HC908AP Family — Rev. 2.5
MOTOROLA

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