MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 148
MC68HC908AP16CFA
Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AP16CFA.pdf
(440 pages)
- Current page: 148 of 440
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System Integration Module (SIM)
9.7 SIM Registers
Data Sheet
148
INT/BREAK
ICLK
IAB
NOTE:
Figure 9-19. Stop Mode Recovery from Interrupt or Break
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
The SIM has three memory-mapped registers:
Freescale Semiconductor, Inc.
•
•
•
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
STOP +1
For More Information On This Product,
SIM Break Status Register (SBSR) — $FE00
SIM Reset Status Register (SRSR) — $FE01
SIM Break Flag Control Register (SBFCR) — $FE03
R/W
IDB
IAB
instruction.
Go to: www.freescale.com
STOP ADDR
Figure 9-18. Stop Mode Entry Timing
Figure 9-18
STOP + 2
PREVIOUS DATA
STOP RECOVERY PERIOD
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
MC68HC908AP Family — Rev. 2.5
SP – 1
SAME
SAME
SP – 2
SAME
SP – 3
MOTOROLA
SAME
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