MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 331

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AP Family — Rev. 2.5
MOTOROLA
MMAST — MMIIC Master Control
MMRW — MMIIC Master Read/Write
MMCRCEF — MMIIC CRC Error Flag
This bit is set to initiate a master mode transfer. In master mode, the
module generates a start condition to the SDA and SCL lines,
followed by sending the calling address stored in MMADR.
When the MMAST bit is cleared by MMNAKIF set (no acknowledge)
or by software, the module generates the stop condition to the lines
after the current byte is transmitted.
If an arbitration loss occurs (MMALIF = 1), the module reverts to slave
mode by clearing MMAST, and releasing SDA and SCL lines
immediately.
This bit is cleared by writing "0" to it or by reset.
This bit is transmitted out as bit 0 of the calling address when the
module sets the MMAST bit to enter master mode. The MMRW bit
determines the transfer direction of the data bytes that follows. When
it is "1", the module is in master receive mode. When it is "0", the
module is in master transmit mode. Reset clears this bit.
This flag is set when a CRC error is detected, and cleared when no
CRC error is detected. The MMCRCEF is only meaningful after
receiving a PEC data. This flag is unaffected by reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Master mode operation
0 = Slave mode operation
1 = Master mode receive
0 = Master mode transmit
1 = CRC error detected on PEC byte
0 = No CRC error detected on PEC byte
Go to: www.freescale.com
Multi-Master IIC Interface (MMIIC)
MMIIC I/O Registers
Data Sheet
331