MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 371

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

18.3.2 Data Direction Register B (DDRB)
MC68HC908AP Family — Rev. 2.5
MOTOROLA
Address:
TxD and RxD — SCI Transmit and Receive Data
T1CH0 and T1CH1 — Timer 1 Channel I/O
T2CH0 and T2CH1 — Timer 2 Channel I/O
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
Reset:
Read:
Write:
The TxD and RxD pins are SCI transmit and receive data pins. Setting
the ENSCI bit in the SCI control register 1 (SCC1) configures the
PTB2/TxD and PTB3/RxD pins for SCI function and overrides any
control from the port I/O logic.
The T1CH0 and T1CH1 pins are the TIM1 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTB4/T1CH0–PTB5/T1CH1 pins are timer channel I/O
pins or general-purpose I/O pins.
The T2CH0 and T2CH1 pins are the TIM2 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTB6/T2CH0–PTB7/T2CH1 pins are timer channel I/O
pins or general-purpose I/O pins.
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
$0005
Bit 7
0
Figure 18-7. Data Direction Register B (DDRB)
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DDRB6
6
0
DDRB5
5
0
DDRB4
4
0
DDRB3
3
0
DDRB2
2
0
Input/Output (I/O) Ports
DDRB1
1
0
Data Sheet
DDRB0
Bit 0
Port B
0
371