HD643303x Hitachi, HD643303x Datasheet - Page 199

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
Bit
Initial value
Read/Write
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
Reserved bit
—
—
7
1
Phase counting mode flag
Selects phase counting mode for channel 2
MDF
R/W
6
0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
FDIR
R/W
5
0
184
PWM4
R/W
4
0
PWM3
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
R/W
3
0
PWM2
R/W
2
0
PWM1
R/W
1
0
(Initial value)
PWM0
R/W
0
0