HD643303x Hitachi, HD643303x Datasheet - Page 204
HD643303x
Manufacturer Part Number
HD643303x
Description
Hitachi Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD643303X.pdf
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Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3
0
1
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3
0
1
8.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit
Initial value
Read/Write
Description
GRB3 operates normally
GRB3 is buffered by BRB3
GRA3 operates normally
GRA3 is buffered by BRA3
Description
Reserved bits
—
—
7
1
—
—
6
1
Master enable TOCXA
These bits enable or disable output
settings for pins TOCXA4 and TOCXB4
EXB4
R/W
5
1
Master enable TIOCA
These bits enable or disable output settings for pins
TIOCA3, TIOCB3 , TIOCA4, and TIOCB4
189
EXA4
R/W
4
1
4
, TOCXB
EB3
R/W
3
1
4
3
, TIOCB
R/W
EB4
2
1
3
, TIOCA
EA4
R/W
1
1
(Initial value)
(Initial value)
4
, TIOCB
EA3
R/W
0
1
4
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