HD643303x Hitachi, HD643303x Datasheet - Page 216

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF
0
1
Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs
Bit
Initial value
Read/Write
Note:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in
*
only under the following conditions:
Only 0 can be written, to clear the flag.
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Description
TFCR)
—
—
7
1
—
—
6
1
Reserved bits
—
—
5
1
201
—
—
4
1
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Overflow flag
Status flag indicating
overflow or underflow
—
—
3
1
R/(W)
OVF
2
0
*
R/(W)
IMFB
1
0
*
(Initial value)
R/(W)
IMFA
0
0
*