HD643303x Hitachi, HD643303x Datasheet - Page 291
HD643303x
Manufacturer Part Number
HD643303x
Description
Hitachi Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD643303X.pdf
(572 pages)
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Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFA5
Address H'FFA7
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
NDR7
R/W
—
—
7
0
7
1
NDR6
Reserved bits
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
—
—
6
0
6
1
NDR5
R/W
—
—
5
0
5
1
276
NDR4
R/W
—
—
4
0
4
1
NDR3
R/W
—
—
3
1
3
0
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
Reserved bits
R/W
—
—
2
1
2
0
NDR1
R/W
—
—
1
1
1
0
NDR0
R/W
—
—
0
1
0
0
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